1. Field of the Invention
The present invention relates to a high-frequency voltage-controlled oscillation circuit, and more particularly, to a high-frequency voltage-controlled oscillation circuit which restrains abnormal oscillations and improves phase noise.
2. Description of the Related Art
A conventional high-frequency voltage-controlled oscillation circuit has been composed of an oscillating amplifier circuit and a phase shifting circuit formed of inductive reactance elements and a capacitive variable reactance element, the phase shifting circuit being formed by connecting the capacitive variable reactance element in series to a third-order π variable high-pass filter.
The conventional high-frequency voltage-controlled oscillation circuit will be described with reference to FIG. 23. FIG. 23 is a diagram illustrating a simplified circuit of the conventional high-frequency voltage-controlled oscillation circuit.
As illustrated in FIG. 23, in the conventional high-frequency voltage-controlled oscillation circuit, the collector and the base of a transistor Q of the oscillating amplifier circuit are connected by a feedback loop, variable-capacitance diodes D2, D3, and D1 are connected in series to the feedback loop, a point between the diode D1 and the diode D3 is connected to one end of a coil L1, which is an inductive reactance element, while the other end thereof is grounded, and a point between the diode D2 and the diode D3 is connected to one end of a coil L2, which is an inductive reactance element, while the other end thereof is grounded.
Here, the diode D3 and the coils L1 and L2 constitute the third-order π variable high-pass filter (HPF: High Pass Filter).
FIG. 24 illustrates the frequency characteristic of an oscillation loop gain of the conventional circuit. FIG. 24 is a diagram illustrating the frequency characteristic of the oscillation loop gain in the conventional high-frequency voltage-controlled oscillation circuit. In FIG. 24, the axis of abscissas indicates frequency and the axis of ordinates indicates gain.
The oscillating frequency in FIG. 24 is set to 700 MHz. Hence, if the phase shifting circuit has a high-pass filter, then an oscillation loop gain may become 0 dB or more at a frequency of 700 MHz or more, leading to a possibility of the occurrence of an unintended oscillation at a frequency of the oscillating frequency.
Further, an oscillation spectrum in an oscillation loop in the case where a prior art is used will be described with reference to FIG. 25 and the levels of harmonics will be described with reference to FIG. 26. FIG. 25 is a diagram illustrating the oscillation spectrum in a conventional oscillation loop, and FIG. 26 is a diagram illustrating the levels of the harmonics.
In FIG. 25, “1” on the axis of abscissas denotes a desired oscillating frequency and “2” and the subsequent numerals denote the orders of high-order harmonics. Referring to FIG. 25 and FIG. 26, it can be confirmed that there is a high-order harmonic level close to the desired oscillating frequency.
The levels of the harmonics are obtained by calculating the deviations from a reference wave (first-order). Further, the distortion rate of each order (=100*10^(deviation/20)) is calculated and the distortion rates of the second-order up to the ninth-order are totalized to obtain the total distortion (%).
Related prior arts have been disclosed in US Patent Application Laid-Open No. US2005/0242896A1 (Patent Document 1), Japanese Patent Application Laid-Open No. 11-154824 (Patent Document 2), Japanese Patent Application Laid-Open No. 2006-279158 (Patent Document 3), Japanese Patent Application Laid-Open No. 2000-228602 (Patent Document 4), Japanese Patent Application Laid-Open No. 2005-086366 (Patent Document 5), Japanese Patent Application Laid-Open No. 06-196928 (Patent Document 6), Japanese Patent Application Laid-Open No. 11-308050 (Patent Document 7), Japanese Patent Application Laid-Open No. 2002-171130 (Patent Document 8), and Japanese Patent Application Laid-Open No. 2003-101344 (Patent Document 9).
Patent Document 1 discloses a specific circuit configuration in FIG. 2 therein. Simplifying this circuit diagram provides one illustrating a circuit having a similar configuration illustrated in FIG. 23. The diodes D1, D2, and D3 and the coils L1 and L2 in FIG. 23 correspond to diodes D3, D2, and D4 to D7, coils TL1 and TL3, and coils TL2 and TL4, respectively, in FIG. 2 of Patent Document 1.
Patent Document 2 discloses that, in a temperature-compensated oscillator, temperature changes in an I/O feedback inductive reactance circuit is compensated for by using a temperature compensating capacitor in an output capacitive reactance circuit of an amplifying element.
Patent Document 3 discloses an amplitude modulator in which a low-pass filter is constituted of inductors L1, L2, and L3, a capacitor C2, and a variable-capacitance diode VD.
Patent Document 4 discloses a resonant line in which a plurality of micro-strip lines is set to a length which causes the reactance between one end of each of a plurality of micro-strip lines and the ground to become equivalently inductive, and the ends thereof are interconnected.
Patent Document 5 discloses a broadband high frequency power amplifier circuit in which a micro-strip line is used as a series impedance function inductance, and the series impedance function inductance is formed into a U-shape pattern.
Patent Document 6 discloses a voltage-controlled oscillation circuit in which a C/N characteristic compensating impedance is formed of a parallel resonance circuit 11 of an inductive element L and a capacitive element C12, and the impedance at a resonance frequency of the parallel resonance circuit is used as a line impedance.
Patent Document 7 discloses a voltage-controlled piezoelectric oscillator in which an amplifier, a piezoelectric vibrator, an expander coil, and a variable-capacitance diode are connected in series, the expander coil being composed of at least two coils.
Patent Document 8 discloses a voltage-controlled oscillation circuit in which a bias resistor R3, which defines a DC bias current, is connected to the emitter of an oscillating transistor, and an impedance control circuit 23 formed of a capacitance component C7 and inductor components L2 and L3 is disposed between the bias resistor R3 and the ground.
Patent Document 9 discloses a frequency shifting high-frequency voltage-controlled oscillation circuit in which the anode of a variable-capacitance diode Dv of a resonance circuit is connected to a ground potential, and a shifting circuit S1 composed of a shifting strip line SL5 and a switching diode Di1 which is connected in parallel to the shifting strip line SL5, a shifting voltage being applied to one end of the switching diode Di1, is disposed in multiple stages between the anode and the ground.    Patent Document 1: US Patent Application Laid-Open No. US2005/0242896A1    Patent Document 2: Japanese Patent Application Laid-Open No. 11-154824    Patent Document 3: Japanese Patent Application Laid-Open No. 2006-279158    Patent Document 4: Japanese Patent Application Laid-Open No. 2000-228602    Patent Document 5: Japanese Patent Application Laid-Open No. 2005-086366    Patent Document 6: Japanese Patent Application Laid-Open No. 06-196928    Patent Document 7: Japanese Patent Application Laid-Open No. 11-308050    Patent Document 8: Japanese Patent Application Laid-Open No. 2002-171130    Patent Document 9: Japanese Patent Application Laid-Open No. 2003-101344